1. Technical Field of the Invention
This disclosure relates to methods of manufacturing semiconductor devices, and more particularly, to a transistor manufacturing method that substantially reduces an annealing process after a local ion implantation of channel adjusting impurity, that controls a thermal ion diffusion of the channel adjusting impurity, and that prevents a junction leakage current.
2. Description of the Related Art
The continuous advancement for increased integration levels in semiconductor devices requires a miniaturization in the size of transistor components. Accordingly, as a length of a channel is reduced from a conventional long channel to a short channel under 0.5 μm, a depletion region of a source/drain region invades the channel, reducing the effective channel length and a threshold voltage. These short channel effects cause gate control to be lost from the transistor.
In order to prevent this short channel effect, a thickness of the gate insulation layer should be reduced, and a channel between source/drain regions, namely, a maximum width of the depletion region below a gate should be reduced. Furthermore, an annealing process may be performed in implanting the impurity ions or in etching the surface of the semiconductor substrate. This annealing can reduce damage to the semiconductor substrate surface and reduce lattice defects caused by the implantation of impurity ions or the etching of the semiconductor substrate surface. This annealing hastens a diffusion of the ion-implanted impurity to change a threshold value or increase a PN junction area or junction density and thus causes a junction leakage current.
FIGS. 1a to 1s are cross-sectional diagrams illustrating a method of manufacturing transistors according to the conventional art.
Referring to FIG. 1a, a pad oxide layer 12, a molding polysilicon layer 14, and a hard mask layer 16 are sequentially formed on a semiconductor substrate 10 doped with a P-type impurity.
Referring to FIG. 1b, a photoresist is deposited on the hard mask layer 16, and is then patterned so as to partially expose the hard mask layer 16 through a photolithography process, and the hard mask layer 16 is selectively etched to expose the molding polysilicon layer 14 through the patterning and to define an active region A.
With reference to FIG. 1c, the molding polysilicon layer 14, the pad oxide layer 12, and the semiconductor substrate 10 are removed partially and sequentially by using the hard mask layer 16 as an etch mask, to form a trench T in the interior of the semiconductor substrate 10.
With reference to FIG. 1d, the molding polysilicon layer 14 and the surface of the semiconductor substrate 10 exposed by a thermal oxide process are selectively oxidized by using the hard mask layer 16 as an oxide stop mask, and a device isolation film 18 is formed in the interior of the trench T through the thermal oxide process. The molding polysilicon layer 14 serves as a buffer layer for mitigating a stress of a volume expansion generated in forming the device isolation film 18. Further, a chemical mechanical polishing or etch back is performed to expose a portion of semiconductor substrate 10 on which the device isolation film 18 is formed, to thus remove all the hard mask layer 16, the molding polysilicon layer 14, and the pad oxide layer 12 and to flatten the semiconductor substrate 10.
In FIG. 1e, active regions A of the semiconductor substrate 10 are individually divided into a cell region X and a core/peri region Y. On the core/peri region Y, a photoresist P or a sacrificial oxide layer is formed, and a P-type impurity, such as boron (B) or BF2, of low dose is selectively ion-implanted into the active region A of the cell region X, to form a third impurity region 22 of low density. The photoresist P or the sacrificial oxide layer formed on the core/peri region Y is removed.
Referring to FIG. 1f, on the entire face of the cell region X and on the semiconductor substrate 10 of the core/peri region Y where a PMOS transistor is formed, the photoresist P or the sacrificial oxide layer is formed and the P-type impurity of low dose such as B or BF2 is ion-implanted thereinto to thus form the third impurity region 22 of low density, and then the photoresist P or the sacrificial oxide layer is removed.
Referring to FIG. 1g, on the entire face of the cell region X and on the semiconductor substrate 10 of the core/peri region Y where the NMOS transistor is formed, a photoresist P is formed. An N-type impurity of low dose such as Phosphorus (P) or Arsenic (As) is ion-implanted into a remaining portion of the core/peri region Y to thus form the third impurity region 22 of low density and to remove the photoresist P.
In FIG. 1h, a thermal oxide process is performed on the semiconductor substrate 10 to form a gate oxide layer 24 with a determined thickness, and a gate electrode 26 is formed on the gate oxide layer 24 by using polysilicon containing a conductive impurity. A conductive metal layer 28 is formed on the gate electrode 26, and a gate upper insulation layer 30 is formed on the conductive metal layer 28 by using a silicon oxide layer etc. The gate electrode 26 can have a conductivity by implanting the N-type impurity into the polysilicon through use of POCl3 precipitation or an ion implantation process.
In FIG. 1i, the photoresist is deposited on the gate upper insulation layer 30, and a photoresist pattern is formed on a gate region G through a photolithography process. Then, the gate upper insulation layer 30, the conductive metal layer 28, and the gate electrode 26 are sequentially removed so as to expose a portion of the gate oxide layer 24 by using the photoresist pattern as an etch mask, and subsequently, the photoresist pattern is removed.
In FIG. 1j, the photoresist P is deposited on an entire face of the semiconductor substrate 10. Next the photoresist P is patterned to expose the cell region X, and an N-type impurity of low dose such as P or As, is ion implanted into source/drain regions S/D exposed by the gate electrode 26 to form a first impurity region 32 of low density. Then the photoresist P is removed.
Referring to FIG. 1k, the photoresist P is deposited on an entire face of the semiconductor substrate 10, and the photoresist P is patterned to expose a formation portion of the NMOS transistor on the core/peri region Y. The N-type impurity of low dose, such as P or As, is ion implanted into the source and drain regions S/D exposed by the gate electrode 26 by using the photoresist P and the gate electrode 26 of the core/peri region Y as an ion implantation mask, to thus form the first impurity region 32 of low density and to remove the photoresist P.
With reference to FIG. 11, the photoresist P is deposited on an entire face of the semiconductor substrate 10, and the photoresist P is patterned to expose a formation portion of the PMOS transistor on the core/peri region Y. The N-type impurity of low dose, such as P or As, is ion implanted into the source and drain regions S/D exposed by the gate electrode 26 by using the photoresist P and the gate electrode 26 of the core/peri region Y as an ion implantation mask, to thus form the first impurity region 32 of low density and to remove the photoresist P. After that, in order to reduce a lattice defect of the silicon semiconductor substrate 10 generated by the ion implantation, an annealing process of a high temperature, e.g., about 800° C., is performed.
In FIG. 1m, a silicon nitride layer is formed on an entire face of the semiconductor substrate 10, and a spacer 34 is formed in a sidewall of the gate upper insulation layer 30 and the gate electrode 26.
In FIG. 1n, the photoresist P is deposited on an entire face of the semiconductor substrate 10, and the photoresist P is patterned to expose a formation portion of the NMOS transistor on the core/peri region Y. Also, an N-type impurity of high dose is ion implanted by using as an ion implantation mask the photoresist P, the gate electrode 26 corresponding to the formation portion of the NMOS transistor of the core/peri region Y, and the spacer, to thus form a second impurity region 36 of high density and to remove the photoresist P.
In FIG. 1o, the photoresist P is deposited on an entire face of the semiconductor substrate 10, and the photoresist P is patterned to expose a formation portion of the PMOS transistor on the core/peri region Y. Also, a P-type impurity of high dose is ion implanted by using as an ion implantation mask the photoresist P, the gate electrode 26 corresponding to the formation portion of the PMOS transistor of the core/peri region Y, and the spacer, to thus form the second impurity region 36 of high density and to remove the photoresist P.
In FIG. 1p, the first interlayer insulation layer 38 is formed of silicon nitride on the semiconductor substrate 10 on which the second impurity region 36 is formed, and is also flattened through the chemical mechanical polishing or etch-back so as to expose the gate upper insulation layer 30 or the spacer 34.
Referring to FIG. 1q, the photoresist P is deposited on the first interlayer insulation layer 38, and is then patterned to expose the first interlayer insulation layer 38 provided on the source/drain regions S/D of the cell region X. Furthermore, the first interlayer insulation layer 38 is removed to expose the dummy gate oxide layer 24 by using the photoresist P as an etch mask. Then, the photoresist P is removed.
With reference to FIG. 1r, the N-type impurity of high dose is ion implanted by using as an ion implantation mask the first interlayer insulation layer 38 of the core/peri region Y, and the spacer 34 and the gate electrode 26 of the cell region X, to thus form the second impurity region 36 of high density on the source/drain regions S/D of the cell region X, and the photoresist P is then removed. After the ion implantation process, an annealing process of high temperature, e.g., about 800° C., is performed.
With reference to FIG. Is, the gate oxide layer 24 on the source/drain regions S/D of the cell regions X and the core/peri region Y is removed, and a pad polysilicon layer 40 is formed of polysilicon containing a conductive impurity on the semiconductor substrate 10. The pad polysilicon layer 40 is flattened through the chemical mechanical polishing (CMP) or the etch back so as to partially expose the spacer and the gate upper insulation layer 30. Then, an annealing process of high temperature, e.g., about 830° C., is performed to reduce a surface defect of the semiconductor substrate 10 corresponding to the source/drain regions S/D under the pad polysilicon layer 40.
Though not shown in the drawing, a second interlayer insulation layer is formed on the pad polysilicon layer 40, and is then removed from the upper part of the source region S to thus form a first contact hole. Also, a bit line contact electrically connected with the pad polysilicon layer 40 through the first contact hole is formed, and a third interlayer insulation layer is formed on the semiconductor substrate 10 involving the bit line contact. The second and third interlayer insulation layers on the drain region are removed to form a second contact hole, and thereon, a storage electrode electrically connected with the pad polysilicon layer 40 of the cell transistor through the second contact hole, a dielectric layer and a plate electrode are sequentially formed, to complete a capacitor of a memory cell.
However, the above conventional transistor manufacturing method exhibits the following problems.
A junction area between the third impurity region formed on the entire active region of the semiconductor substrate and the first impurity region formed on the source/drain regions, becomes extended in a subsequent process. Furthermore, the channel adjusting impurity is diffused into the first impurity region, causing the junction area to be widened and a junction leakage current to increase, due to several annealing processes, such as an annealing process performed after the ion implantation of the channel adjusting impurity in forming the third impurity region, and such as an annealing process of high temperature performed after the formation of the pad polysilicon layer.
Embodiments of the invention address these and other disadvantages of the conventional art.